Error: Conflict PLL, Custom PHY IP 4 Lane GE with Quartus Prime Standard 30-Day Free Trial

Hi Le_vietnam,

May I know the full device part number you are using?

According to this error message, it seems the placement of the pins violated some design constraints.

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#msgs/msgs/ehssi_hssi_constraint_check_6pack_msg.htm

For different usage of transceiver, you need to follow specific placement guidelines. For example, you can find the guideline of PCIe in this chapter of Cyclone V Device Handbook: Volume 2: Transceivers.

https://www.intel.com/content/www/us/en/docs/programmable/683586/current/pcie-supported-configurations-and-placement.html

Best Regards,

Xiaoyan