EP4CE parallel signal's timing chart

Hi Pochi,

Which IP that you are using?

Regards,

Adzim

Hi Pochi,

I think we are discussing on the same topic in this thread: https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Cyclone-IV-SDR-SDRAM-DDR2-Timing-Parameter-Settings/m-p/1640438#M28524

Therefore, I will transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Regards,

Adzim