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Ankit_P_Intel's avatar
Ankit_P_Intel
Icon for New Contributor rankNew Contributor
5 years ago

Enabling Intel® Stratix® 10 H-Tile and L-Tile Avalon® Memory Mapped (AvalonMM) Hard IP for PCI Express* on S10-DX kit

HI All I have https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s10-dx.html kit with me and I am planning on enabling simple DMA over PCIe design on ...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi,

May I request to open an new thread for the above question , please.

  • Ankit_P_Intel's avatar
    Ankit_P_Intel
    Icon for New Contributor rankNew Contributor
    5 years ago
    You can close this thread for now; I think I have got the user guide for p time IP I was looking for doe S10 DX kit