Enabling Intel® Stratix® 10 H-Tile and L-Tile Avalon® Memory Mapped (AvalonMM) Hard IP for PCI Express* on S10-DX kit

i have started following the use guide https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-ptile-pcie-avmm.pdf

following question

1. On pg 16 - step 12 c - for target development kit i see option for "Intel Stratix 10 DX P-Tile ES1 FPGA Development Kit". is this kit same as https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s10-dx.html? i have this kit and when i google "Intel Stratix 10 DX P-Tile ES1 FPGA Development Kit" it couldn't find anything and only pointed s10-dx kit link as above.
2. i went ahead following the instructions but my compilation failed with these errors. can you help me solving these errors?