Forum Discussion
MHamz1
New Contributor
New ContributorEfficient way of making counter
What is the efficient way of making counters in VHDL when the source clock is in range of 400MHZ
ak6dn
Regular Contributor
Regular ContributorGoogle LFSR-based counter. In just about any FPGA 400MHz is too fast for a binary counter of any reasonable size (ie, 8-16 bits or more).
RRomano001
Contributor
ContributorHi ak6dn, also ring counter, Johnson counter, Möbius counter.
They are cases of LFSR but not for sure are mentioned by LFSR theory.
Regards.
