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MHamz1's avatar
MHamz1
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7 years ago

Efficient way of making counter

What is the efficient way of making counters in VHDL when the source clock is in range of 400MHZ
ak6dn's avatar
ak6dn
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7 years ago

Google LFSR-based counter. In just about any FPGA 400MHz is too fast for a binary counter of any reasonable size (ie, 8-16 bits or more).

  • RRomano001's avatar
    RRomano001
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    6 years ago

    Hi ak6dn, also ring counter, Johnson counter, Möbius counter.

    They are cases of LFSR but not for sure are mentioned by LFSR theory.

    Regards.