Petkov_Alex
Occasional Contributor
Occasional ContributorDynamic reconfiguration Native Phy S10 with embedded streamer
Hello. I try to simulate NATIVE PHY and ATX PLL for S10. I use 2 profiles switching from GX channel to GXT channel and ATX PLL to as mentioned in document how to use this feature (UG for L-tile S10).
So I created IP cores, Sim files for them and TestBench for it. I wrote Read-modify-write module.
But when I simulate design after my module writes to embedded streamer address 0x540 in several clocks waitrequest goes high, that ok, i know specification for avalon mm bus... Than I begin reading address 0x541, and waitrequest never goes low.
So simulation is strange, I explain. When for example I write to digital or analog reset addresses, everything goes good. But when i write to address embedded streamer or static polarity inversion, reconfiguration avalon waitrequest stuck at high and when I read or write next, it never goes low.
P.S. Quartus Pro 21.4, QuestaSim 10.7c
So I created IP cores, Sim files for them and TestBench for it. I wrote Read-modify-write module.
But when I simulate design after my module writes to embedded streamer address 0x540 in several clocks waitrequest goes high, that ok, i know specification for avalon mm bus... Than I begin reading address 0x541, and waitrequest never goes low.
So simulation is strange, I explain. When for example I write to digital or analog reset addresses, everything goes good. But when i write to address embedded streamer or static polarity inversion, reconfiguration avalon waitrequest stuck at high and when I read or write next, it never goes low.
P.S. Quartus Pro 21.4, QuestaSim 10.7c
- Sorry for my late answer, I read document one more time, and understand, that every reconfiguration of S10 Native Phy begin from disable background calibration and end with enable background calibration if it needed. Thanks
