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He4Forum's avatar
He4Forum
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Downtrain to PCIe Gen3x8 when generating Quartus design with Avalon-MM+ IP for S10 GX dev kit

Avalon® memory mapped Intel® Stratix® 10 Hard IP+ for PCI Express* Solutions User Guide shows that Avalon-MM+ IP can support Gen8 x 16 for PCIe. When I genetate a design with the IP, I find ...
skbeh's avatar
skbeh
Icon for Contributor rankContributor
3 years ago

Hi He Xu

Sorry please ignore the previous reply. I noticed you are using AvMM+ IP for PCI Express and generated the gen3x16 example design.

To determine if your example design is link-up as Gen3x8 or Gen3x16, kindly use Signaltap to monitor the value of currentspeed_o[1:0] and lane_act_o[4:0]


currentspeed_o[1:0] indicate the current speed of the PCIe link. The following encodings are defined:

2'b00 : Undefined

2'b01 : Gen1

2'b10 : Gen2

2'b11 : Gen3


lane_act_o[4:0] indicate the number of lanes that are configured during link training. The following encodings are defined:

5'b0 0001 : 1 lane

5'b0 0010 : 2 lanes

5'b0 0100 : 4 lanes

5'b0 1000 : 8 lanes

5'b1 0000 : 16 lanes


He4Forum's avatar
He4Forum
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hi skbeh,

Sorry, I am a newbie for Quartus Software. Do you mean I should use the Signal Tap Logic Analyzer?

After I clicked on the Signal Tap, it shows like this.

Then what should I do to monitor the value of currentspeed_o[1:0] and lane_act_o[4:0] as you told me?

Thanks.