Does the logic inside flash memory devices require a power down after each WRITE operation?

Hello Arnaud, Thank you for taking the time to reply me. I’m trying to resolve the issue by programming my flash using another methods: 1- Although my purpose is to program my flash with an executable application and I do not need to program the FPGA configuration into it but I’ve tried to program my flash using JIC file , I generated the JIC using only SOF file, after resetting the board , the FPGA has been successfully configured but I can’t run nothing with the Flash because it was fully written by the JIC configuration. For this, my question is : should the EPCQ size be faithful to the qsys system configuration (I’m using a board that has flash EPCQ-L 1024 and for specific reasons I’m using a flash controller for EPCQ-L256)? 2- I’ve tried to program my flash using the Nios II flash programmer with an executable software ELF file, but I found the following error: 3- I’ve tried also to use the Nios II shell commands with the debug option but I’ve got errors.. Kindly, check the attached file given here below I’m waiting for your directions, thank you. Best regards, CR