Does the logic inside flash memory devices require a power down after each WRITE operation?

Hi Anand,

Thank you for your reply.

1. I am trying to access in read and write my EPCQL-1024 using the Quartus Prime version 16.0. I have the Altera Serial Flash Controller I configured in QUAD mode connected from its avl_csr and avl_mem to the NIOSII.
2. As the NIOSII is booting from an onchip memory I think that it's no need to program the flash memory with jic file. Tell me please if I'm missing something. I have tried to access in read and write the EPCQL registers (STATUS, Device ID) and the controller registers FLASH_ISR, or FLASH_IMR, protect sectors also and it have been successful.
3. Here lies my problem: after WRITE operations (erase sector or write bytes), the device does not respond to any instruction except the READ STATUS REGISTER, although the read status register value indicates that there is no erase or write cycle in progress (the WIP bit is 0 so the write operation is completed). I need to power off the chip then power on and reload my .sof to get values back from my EPCQL and the data read back after power down being as expected.

Kindly, check the attached file given here below, you will find screenshots of my system to show you connections I have made and running results. I’m wondering if the logic inside flash memory devices requires a power down after each WRITE operation.

Your reply will be appreciated, thank you in advance.

Best Regards,

CR