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Sushmita's avatar
Sushmita
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Does Interface Templates option from Platform Designer > new component provides the RTL (verilog/vhdl) code apart from the skeleton hdl portlist?

Hi, I was going through the following video about Avalon interface on platform designer. Regarding the same, the below points have been mentioned: a) template option in new component can be used to...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

It's just the skeleton. You have to fill in the functionality. When you click "Create synthesis file from signals", you should see the template that you can then save and edit.

#iwork4intel

Sushmita's avatar
Sushmita
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi @sstrell​

I have found the templates for Avalon mm master and slave interfaces in .v format from the below given links. They are dated back to 2008. For example, mm master code provided in the zip file, uses FIFO,some control signals.

Can those templates be directly used in our custom modules as is to perform basic interface functionality or we have to customize the code as per used and unused signals?

LINKS:

1) master:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-mm.html

2) slave:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-memory-slave.html