Does Interface Templates option from Platform Designer > new component provides the RTL (verilog/vhdl) code apart from the skeleton hdl portlist?

Okay.

Thanks for the reply.

Hi @sstrell​

I have found the templates for Avalon mm master and slave interfaces in .v format from the below given links. They are dated back to 2008. For example, mm master code provided in the zip file, uses FIFO,some control signals.

Can those templates be directly used in our custom modules as is to perform basic interface functionality or we have to customize the code as per used and unused signals?

LINKS:

1) master:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-mm.html

2) slave:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-memory-slave.html

HI,

Thanks for replying!

yes, I have seen the document. I have downloaded the zip file and opened in qsys.

But after following instructions as told in page 188, and i try to save changes, it shows that the example design is not writable. So i couldnt generate the HDl.