Does Interface Templates option from Platform Designer > new component provides the RTL (verilog/vhdl) code apart from the skeleton hdl portlist?

HI,

Thanks for replying!

yes, I have seen the document. I have downloaded the zip file and opened in qsys.

But after following instructions as told in page 188, and i try to save changes, it shows that the example design is not writable. So i couldnt generate the HDl.