Do all EP4CE55F23 devices have the exact same footprint, pin names, and are they interchangable?

Hi,

My name is Hazlina and I am the Senior Manager of Applications Engineering team for FPGA/CPLD based product. FYI, we support technical questions for FPGA/CPLD products only through the community portal at https://forums.intel.com/s/ which is this portal. So you have come to the right place!

The response that you got earlier was through a different support channel - so the agent responding to you can only provide you with a canned response and they were supposed to redirect you to here, unfortunately didn't happen in your case. So I apologize for the mishap.

I will be assigning an engineer to your case shortly so that he can take a look at your questions and provide a response accordingly. Thanks.

I forgot to mention that we do not provide/generate PCB footprint symbol to customers. Customers have to generate this by themselves.

But we do provide ORCAD schematic symbols and will be able to address your questions on the ORCAD schematic symbols accordingly.

We can also point to you the right pin list file so that you can generate the PCB symbols and ORCAD schematic symbol (if you wish to do so). Thanks.

Hello

I’m from Applications Engineering support team for FPGA/CPLD helping you regarding your issue.

1) Regarding you question on the definition of Intel FPGA part number and device code information, you can refer to below doc link (page 12, figure 1-3)

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-51001.pdf

By referring to figure 1-3 and figure 1-2, you can see, the last 3 digit of FPGA part number just specify the temperature and FPGA core performance speedgrade. Hence, it won’t affect the pin location or pin function of the FPGA.

2) Where do download the pinout file for FPGA (EP4CE55F23) and which column to refer in the pinout file? You can refer and download EP4CE55 pinout file from below link

https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.htm

FPGA is using part number as reference for pin indication. In your case, you are planning to use EP4CE55F23A7N. By referring to figure 1-3, FPGA is using part number F23 = 484 pins. That means you needs to refer to column F484 of the pinout file.

3) Lastly as mention above, we no longer support PCB footprint anymore, it is replaced with Cadence Capture CIS schematic symbol in (olb.) format.

Cadence Capture CIS schematic symbol is available through https://www.intel.com/content/www/us/en/programmable/support/support-resources/download/board-layout-test/pcb/pcb-cadence.html

We apologize for the inconvenience and difficulty that you have. We hope that this update will clears up this matter.

Hi,

Thank you for the details!

I had already worked through this with great difficulty yesterday, and found all you mention here, but I do appreciate the details as it confirms what I found is correct.

I would like to ask if you can please share a picture of the FPGA package, with the pin names visible, so that I can choose/create the correct footprint, with the pins in their correct locations?

Are the pin labels in a standard format, such as rows alphabetical and columns numbers, and starting in the upper right hand corner?

Thanks!

John

Hi Sir

For the FPGA package, with the pin names visible you can find at https://www.intel.com/content/www/us/en/programmable/support/support-resources/download/board-layout-test/pcb/pcb-cadence.html example: for EP4CE55F23 you can search under Device Family=Cyclone IV E and Part Number= EP4CE55