Disappointed with Cyclone III FPGA Development Kit

Hey Simon,

Sorry to hear you've had a bad impression of the kits so far.

I have a slightly different approach when it comes to kits. I assume the example code will be junk, so start from scratch. I create a design called 'basic' that implements the bare-minimum in VHDL; generally a clock divider and blinking LEDs. There is at least two files you need; the design VHDL or Verilog and a constraints file. The contents of the constraints file can be minimized by using the GUI to create a new project, select the FPGA on your board, and then source a Tcl script that contains just the pin assignments. As you get more familiar with the design tools, you can create more complex scripts, or ask me, and I'll post examples.

If you do not see the Tcl console under Quartus, use View->Utility Windows->Tcl Console to bring it up.

Where can you get the correct pins? I first get copy of the schematic, and then find a fairly complete example that comes with the board. I take that example and use the Quartus 'Project->Generate Tcl File for Project' option to generate the Altera script for the design. I then cut-and-paste that file into Tcl procedures, in your case, you could just delete everything except for the pin assignments. Then go through each page of the schematic and find the corresponding nets on the FPGA. Rename pins to something sane, eg. DDR interface signals can all be prefixed with ddr_xxx, and add missing pins.

Before you download to the board, use the Assignments->Pin Planner window to see that all signals have been assigned. Check the I/O voltages on that page with respect to the voltages on the schematic. You might also need some voltage constraints on the I/O.

Take a shot at doing this, and if you get stuck, ask questions. I'll send you code if you like, but I don't want to spoil the excitement for you, of figuring out how it works.

Cheers,

Dave