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It will be great, If anyone can give some insight for this issue.
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The most likely problem is a timing issue. You can investigate using several methods;
1. Ensure that the interface has timing constraints
a) The project has an SDC file and that file includes timing constraints for the SSRAM interface.
b) The project compiles with no warning messages from TimeQuest.
c) TimeQuest can be used to view the SSRAM interface signals
If the developers of the examples have "cut" the paths to the SSRAM, then you will not get TimeQuest warnings, but you will also not be able to analyze the SSRAM interface signals in TimeQuest.
2. Review the TimeQuest timing constraints.
Make sure they make sense relative to the data sheet, and that the pin capacitance settings reflect the multiple loads on the shared Flash/SSRAM bus.
3. Change the SSRAM interface to use a clock from a PLL.
Send one PLL output clock to the SSRAM and another to your FPGA I/O registers. Sweep the PLL phase for the clock output used by the FPGA or the SSRAM (but not both at the same time), either by resynthesizing the design, or by using an ALTPLL_RECONFIG component. This will allow you to determine the interfacing timing margin.
Cheers,
Dave
Honored Contributor
