DE2-115 Multiplexed SRAM

Using TerASIC SRAM component (tested and verified) and wanted to add a second Avalon MM slave. Created a second component with a MM master and a signal to control the mux selection. SRAM component is attached to NIOS CPU with address_master and data_master and attached to my component via SOPC builder. Mux control seems to work. When I select CPU, i can read and write SRAM from the CPU. However, when I try to access via my component, I get all 0xFF.

Basic design of my components memory master is this (all I want to do is read the SRAM. It is inside an always loop based on system clock:

state 0:

chip_select_n <= 0;

write_n <= 1;

address <= {12'b0,address_to_read);

read_n <= 0;

lbe_n <= 0;

hbe_n <= 0;

go to state 1

state 1:

go to state 2

state 2:

my_data <= readdata;

chip_select_n <= 01;

write_n <= 1;

address <= 32'bz

read_n <= 1;

lbe_n <= 1;

hbe_n <= 1;

Any thoughts on why I shouldn't be able to read on the non-CPU side of the MUX? Is my configuration valid given the Avalon MM paradigm.

Thanks, in advance,

ME