DE1SOC VGA

Question

Hi everyone,I’m working with the DE1-SoC board and I’m having trouble configuring the VGA output to be controlled from the HPS side. Most of the examples I’ve found online are outdated and use IP blocks that are no longer available in the latest versions of Quartus (in Platform Designer).My goal is to be able to draw or write directly to memory from the HPS and have the output shown on the VGA. Unfortunately, I haven’t found any updated documentation or working examples.Has anyone managed to do this recently? Could someone share a working .qsys project that is compatible with the latest Quartus Prime Lite versions?I’m attaching the .qsys file I’ve put together so far, in case someone can take a look and point out what I’m missing or doing wrong.Any help would be greatly appreciated even just an explanation of the necessary modules (frame buffer, clocks, HPS-to-FPGA bridge, etc.) would be super helpful.Thanks in advance!

jeet14 · Answer

Hi,Thank you for reaching out.At the moment, Altera does not provide any VGA solution.However you may refer to the example design in the below link for your reference:Terasic - DE1-SoC-MTL2 User Manual - https://www.terasic.com.tw/cgi-bin/page/archive_download.pl?Language=English&amp;No=930&amp;FID=61e19486e58f69eebbae077500c99f57RegardsTiwari

jeet14 · Answer

Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

fvm · Answer

Hi,looking at DE1-SoC demonstrations, there's no HPS based VGA design, just pure FPGA TV box project. It's using standard IP and can be still compiled by to recent Quartus versions.To interface VGA controller with HPS, you'd connect left side of frame buffer.

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DE1SOC VGA

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