Forum Discussion
hsyn
New Contributor
New ContributorDe10-Nano GHRD UNSTABLE
Hello,
I created a new design with DE10_NANO_SoC_GHRD sample project. There are 2 new ip-cores which are made by me (bw_flash_loader and bw_flash_loader_pin_router) in new design.
The bw_flash_lo...
hsynNew Contributor
New ContributorHi,
I recompiled all design again but nothing changed. It worked unstable.
I didn't add any constraint for spi and jtag pins.
Which subject should I focuse to? Platform Designer(connections and parameters) , timing constraints , Assignment Editor Parameters (current strength, slew rate, etc.) , own ip cores or verilog codes , noise and reflections , etc.
hsynNew Contributor
New Contributorif there is a problem about timing constraints, in this case, it does not work stable with high spi frequencies, does it? But, it didn't work well(not stable) with low spi frequencies also.
- EBERLAZARE_I_Intel
Regular Contributor
Hi,
It seems that this might be a timing issue after adding those components mentioned.
You need to properly constrain your design.
