New Contributor
Regular ContributorHi,
The causes may vary, since you have changes in the GHRD which is connected to the HPS, you need to recompile all the design.
E.g recompile in the Platform designer and Quartus, then recompile the device tree, preloader and Uboot.
New ContributorHi,
I recompiled all design again but nothing changed. It worked unstable.
I didn't add any constraint for spi and jtag pins.
Which subject should I focuse to? Platform Designer(connections and parameters) , timing constraints , Assignment Editor Parameters (current strength, slew rate, etc.) , own ip cores or verilog codes , noise and reflections , etc.
New Contributorif there is a problem about timing constraints, in this case, it does not work stable with high spi frequencies, does it? But, it didn't work well(not stable) with low spi frequencies also.
Regular ContributorHi,
It seems that this might be a timing issue after adding those components mentioned.
You need to properly constrain your design.
