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Altera_Forum
Honored Contributor
Honored ContributorDE1-SoC SDRAM Timing Parameters For QSYS
Is there a definitive source for the timing parameters to enter into QSYS for the DDR3 SDRAM on the HPS? Regards, Tony.
Altera_ForumHonored Contributor
Honored ContributorHi, Tony, actually, DDR3 is controlled by HPS, no need for DDR3 into QSYS, anyway, for SDRAM timing parameters, please refer to the pdf file below from your CD.
\Datasheet\DDR3 SDRAM\43TR16256A-85120AL(ISSI).pdf
