Forum Discussion
Altera_Forum
Honored Contributor
12 years agoNVM, got the sdram working, the problem was i needed to set the Qsys component CPU Nios II/e with reset vector and exception vector set as: epcs, and onchip_memory respectively. (I am also using the university IP DE series clocks to do the -3ns phase shift required for SDRAM.
To reduce program size I unchecked enable_c_plus_plus and checked enable_small_c_library in BSP editor. this reduced program size by 2KBytes. Everything still works, it flashes and loads firmware fine. There is however a problem that if i edit application and BSP properties and set optimization level to 2 , after i use flash programmer the system does not seem to load firmware. I wonder why, a bug?