Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

DE0-NANO voltages and current parameters

Hello everyone A few day ago i got my first FPGA board, DE0-NANO. First of all, based on user manual, i created a pin assignment file in *.csv format. After "import assignments", i see t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The I/O voltage of 3.3V is fixed for all banks of DE0-Nano by design. The difference between LVCMOS and LVTTL is in the mapping of current strength numbers to hardware drive strength.

For Cyclone III and Cyclone IV, drive strength at 3.3V and 3.0V has been restricted in the Quartus software, apparently to protect the chip against overload or self generated overshoots. The lowest drive strength LVCMOS 2 mA should be suitable for most applications. LVTTL 4 mA results in almost the same phsyical drive strength, the different numbering is due to respectived level specifications. If you need maximum drive strength for some reason (e.g. to generate fast clock edges), select LVTTL 8 mA. Please consider that the output short circuit current also doubles and the risk to damage the ship in case increases.