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Hallo
I am using DE0-NANO board for my project and i get the following warning from the pin out voltage. I am using 3.3 V LVTTL for all the pins and 8 mA
I am attaching my pin out file.
Warning (169177): 6 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces.
Info (169178): Pin clk_enable uses I/O standard 3.3-V LVTTL at N9
Info (169178): Pin clk uses I/O standard 3.3-V LVTTL at R8
Info (169178): Pin reset uses I/O standard 3.3-V LVTTL at E1
Info (169178): Pin BCLK uses I/O standard 3.3-V LVTTL at B7
Info (169178): Pin WS uses I/O standard 3.3-V LVTTL at A7
Info (169178): Pin Input uses I/O standard 3.3-V LVTTL at C8
This warning doesn't have any effect on the complitation, i am just concerned if it has any effect on the hardware i am connecting to. The input coming from my external hardware to development board GPIO pins are 3.3 V LVTTL
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These are all completely normal INFO lines for this board. All the I/Os are in a 3.3V bank (not changeable). You can alter the class from LVTTL to LVCMOS, and change drive strength, etc as required via commands in the .qsf file for the design. 3.3V LVTTL at 8ma is the typical setup. Nothing to worry about.
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