DE0-CV, QSYS, execute program from SDRAM instead of onchip (instruction master S1..)

Hello Galfonz,

Thank you for answering my question. I spent a lot of time (i mean days) with the altera tutorials. I could not get the SDRAM operational on my board. Until the moment i took the demo application from Terrasic and saw that the PLL that drives the SDRAM according to the altera university is not the same as the configuration on the demo cd. So i got the sdram working (data only) based on a redo from scratch based on the terrasic project. I read somewewhere that Terrasic changed the type of SDRAM on the desing at a certain time. So might explain my results.

Based on that working design id did what you proposed:

- remove on chip ram from the project.

- assign base adress 00 to SDRAM

- update ram layout

- set memory vectors in processor according to new config (select S1. ... ) adress is updated automatically

- compile / save / generate QSYS (no errors, some warnings about older type of Nios II processor core)

- close qsys and compile verilog in quartus.

- download project on DE0-CV (it downloads clearly because my Verlog clock tutorial program i put in the EPROM is no longer showing on the 7seg).

- start nios II build tools for eclipse

- generate BSP -> error: severe: bsp not valid

- delete projects in eclipse and restart wizzard

- open SOPC generated by QSYS/Quartus: (checked the compile date and time, so it is the right one)

- select hello world application. (project name hello world application)

- clean BSP + BUILD All -> Build Finished OK (output shows files were generated)

- build Project -> build finished (output shows that files were generated)

- right click on project, debug AS select NIOS II and go

=> It works.

Thanks a lot!

John.