Please accept my apology for the delay in response due to public holiday in my region.
I've compiled your project and see the fitter error. Below is what I’ve been analyzed.
1) Top level file:
I noticed that there is a mismatch between the DQ width in the top level file set in the project (s10_ddr4_top.v) and the DDR4 IP top level file (ddr_ip.v). I am not familiar on the modified top level file thus not able to edit it. Please help to change this accordingly. Refer below:
a) s10_ddr4_top.v = 72 bits --> inout wire [71:0] mem_dq,
b) ddr4_ip.v = 64bits --> inout wire [63:0] mem_dq
2) Assignment Editor:
Pins is assigned for 72 bits data. Please remove extra 8 DQ data ( DQ [ 71:64]) in the QSF file and save.
Add/Cmd pins location: In the design, Add/Cmd pins were assigned to Bank 2L . The reason Fitter compilation failed is due to BANK 2L are not middle of IO bank where 64 bits DDR4 interface is placed. EMIF pin placement requirement required Address/Command/Control pin be placed in the middle of IO bank. This also mentioned in the Stratix 10 EMIF User guide.
Example as below.
EMIF IO bank usage 3A, 3B, 3C : Address pin need to be in 3B
EMIF IO bank usage 3B, 3C, 3D : Address pin need to be in 3C
EMIF IO bank usage 2L, 2M, 2N : Address pin need to be in 2M
Please change Add/Cmd pin to Bank 2M. To avoid any conflict or accidently placed the pins in wrong location, I suggest that you remove all the location assignment and only assign one DQ pin to Bank 2L ( for example : mem_dqs[0] to Bank 2L) and one Addr pins to Bank 2M ( for example: mem_a [0] to Bank 2M) and let Quartus auto-fit the rest of them.
It worked for me in a simplified example design test case project. Please try it for your your project pinout and let me know if it works OK. Hope this helps.😊
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