Forum Discussion
ContributorDDR4 compile conflict with existing constrains
Hi David,
I can see the alert_n pin that you disabled.
Actually the alert_n pin configuration is in the EMIF IP.
When you open the EMIF IP in IP Parameter Editor, under the Memory tab, in Topology section, there is a ALERT# pin placement option.
The EMIF IP will reserve the location that you have set for the alert_n pin.
In your project, I can see that you set it to I/O Lane with DQS Group 0.
So the pin location should be in the Bank 2L where there is your DQS Group 0 - 3.
Because the alert_n pin is not been set by the user, the Quartus will set it for you.
In this case, I can see that the Quartus has set it to pin C28.
So now you can change the pin location from E35 to C28 or just let the Quartus set it for you.
I generate the .tcl file from the Pin Planner in case you want to refer the pin location that have been changed.
But I also share the .qsf file to ease your work.
Don't worry on how to use it.
It's just for reference purpose.
I'm sorry for confusing you.
Please let me know if you're still having trouble with it.
Thanks,
Adzim
Regular ContributorHi David,
I can compile the project successfully by relocating the pin locations in DQ Group.
I can see that the pins have been assigned to wrong group which cause the errors.
I've reassigned all mem_dbi_n pins to the right location.
I also have assigned the location for dqs pins and some dq pins which are missing and misplace in the wrong Bank.
I've attached the tcl file from the pin planner and qsf file for your reference.
Please let me know if you're facing some problems with it.
Thanks,
Adzim
ContributorHi Adzim
I am very grateful for the detailed touch of my project, it is a miracle, it would take me weeks to figure this out. this is called support instead of like other people told me to read the manual or take the training.
there are still two things, one is directly related one is for basic knowledge suggestion.
for the qsf file, this is still one line that I commented which should be enabled.
#set_location_assignment PIN_E35 -to mem_alert_n[0].
I don't really know that is mem_alert_n[0] for. but it ME_ADDR_CMD[29] (N4 Pin on the Hilo memory slot). once uncomment this line, the compilation will fail again, why by adding just one more pin will fail the compilation.
Info(14710): The I/O pad mem_dqs[0] is constrained due to: User Location Constraints (PIN_B26)
Info(14710): The I/O pad mem_alert_n[0] is constrained due to: User Location Constraints (PIN_E35)
Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints . Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error(175011): Conflicting region assignments found for DQ_GRP, which is within External Memory Interfaces Intel Arria 10 FPGA IP jesd204b_emif_0_altera_emif_1920_n6nqnfq
Info(175028): The DQ_GRP name(s): jesd204b_inst|emif_0|emif_0|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst_DQ_GRP_1
Info(175014): Component must be in region from (78, 196) to (78, 207) due to the following assignment(s)
Info(14710): The I/O pad mem_dqs[0] is constrained due to: User Location Constraints (PIN_B26)
Info(175014): Component must be in region from (78, 169) to (78, 180) due to the following assignment(s)
Info(14710): The I/O pad mem_alert_n[0] is constrained due to: User Location Constraints (PIN_E35)
Info(14709): Each constrained I/O pad is contained within this DQ_GRP
Error(175011): Conflicting region assignments found for DQ_GRP, which is within External Memory Interfaces Intel Arria 10 FPGA IP jesd204b_emif_0_altera_emif_1920_n6nqnfq
Info(175028): The DQ_GRP name(s): jesd204b_inst|emif_0|emif_0|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst_DQ_GRP_1
Info(175014): Component must be in region from (78, 196) to (78, 207) due to the following assignment(s)
Info(14710): The I/O pad mem_dqs[0] is constrained due to: User Location Constraints (PIN_B26)
Info(175014): Component must be in region from (78, 169) to (78, 180) due to the following assignment(s)
Info(14710): The I/O pad mem_alert_n[0] is constrained due to: User Location Constraints (PIN_E35)
Info(14709): Each constrained I/O pad is contained within this DQ_GRP
Info(175028): The DQ_GRP name(s): jesd204b_inst|emif_0|emif_0|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[0].lane_gen[0].lane_inst_DQ_GRP_1
Info(175014): Component must be in region from (78, 196) to (78, 207) due to the following assignment(s)
Info(14710): The I/O pad mem_dqs[0] is constrained due to: User Location Constraints (PIN_B26)
Info(175014): Component must be in region from (78, 169) to (78, 180) due to the following assignment(s)
Info(14710): The I/O pad mem_alert_n[0] is constrained due to: User Location Constraints (PIN_E35)
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second question is more generic, I don't know how to use the .TCL file. during the training I know in the command window, by running TCL script, I can run some complicate simulation. in this case, how can I use this TCL file, you can just give a link of the TCL tutorial, I need learn this section carefully.
Best Regards,
David
