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Honored Contributor
Honored ContributorDDR3 Termination scheme
Hi, In Stratix IV GX FPGA Development Kit Board(EP4SGX230KF40) there are two DDR3 interface. In 128 Mbytes DDR3 TOP interface, no termination are used for address and control signals. Is ...
Altera_ForumHonored Contributor
Honored Contributorhi all!!!
i am developing a board with a cyclone V FPGA and a DDR3 .......... I would like to know if address, comand and control need a ternination escheme, i am using only one memmory DDR3. i know DDR3 use fly-by termination scheme , but if don´t need i don´t do...... anyone cam help me?? Franz Wagner
