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Altera_Forum
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14 years ago

DDR3 Termination scheme

Hi, In Stratix IV GX FPGA Development Kit Board(EP4SGX230KF40) there are two DDR3 interface. In 128 Mbytes DDR3 TOP interface, no termination are used for address and control signals. Is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The termination as you mean is on board termination?

As i know, SIV device have ODT(on device termination) feature that can replace the on board termination.