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Altera_Forum
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14 years ago

DDR3 Termination scheme

Hi, In Stratix IV GX FPGA Development Kit Board(EP4SGX230KF40) there are two DDR3 interface. In 128 Mbytes DDR3 TOP interface, no termination are used for address and control signals. Is ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Basically, if the clk wavelength/4 is longer than a wire of the clk, then no external termination can be used. Again, I am not sure what I am posting, just some overheard stuff.