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Altera_Forum
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12 years ago

DDR3 A and DDR3 B - Cyclone V Dev Kit

Hi, I'm trying to deal with both DDR3 A and DDR3 B of the Cyclone V Dev Kit. Has anyone already tried to use both DDR3 A and B in the same design ? I met a problem to find out exact pins fo...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Hi, we are currently implementing DDR3A & B on the Cyclone V GX dev. board.

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Has anyone already tried to use both DDR3 A and B in the same design ?

I met a problem to find out exact pins for OCT signals.

(only pin_ak13, wheras I need two pins).

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You are correct in that the only pin for the OCT signals is PIN_AK13. To solve this you need to go into your QSYS system and in the DDR3 configuration dialogs, you need to enable OCT sharing. Configure one of the DDR3 blocks as Master and the other as slave. The master will have an OCT signal to export and an OCT SHARING conduit that must be wired to the slave DDR3 block's OCT SHARING conduit interface. This should take care of that....