DDR3 - CYCLONE V SOC FAILING ON HARDWARE

Dear MHada,

I totally understand the pain your are facing.

Yes, we did experienced this timing issue that also caused the calibration failure. But in this case, I assume you did check and verify that the DDR3 settings and timing parameters are match the device specs on the datasheet. In other word, the DDR timing in Quartus is clean as per you said, you did check and verify all the components and connections. Plus, the DDR3 is passing on the other boards which make me strongly believed it is not due to the DDR3 IP. There are two possibilities that I can think of here is either the issue due to board/board setting entered in Quartus or the FPGA itself. Before you swap the FPGA, you may want to try to test on below recommendation and see if this make any changes to your issue.

I see the calibration failure you are facing based on the report is at Stage 1.

SEQ.C: Error Stage : 1 - VFIFO

SEQ.C: Error Substage: 1 - GUARANTEED READ

which is usually due to an address and command skew issue, with respect to the memory clock (CK), at the memory device.

A recommended measurement is:

• At the memory device, using balanced scope probes, measure the memory clock rising edge and the chip select low pulse.
• Verify the setup and hold time is reasonably balanced.
• If not, there may be setup up or hold violations on the address/command which typically results in a “Guaranteed Read Failure” error message.
• If the HPS SDRAM GUI has Dynamic ODT set to an RZQ/# value, set it to disabled and set the Nominal ODT to the required termination value, recompile, and see if this makes any difference to your tests.

Also, just a quick check, make sure you run board simulation and enter the correct board skew. If no, please use the latest board skew parameter tool to accurately calculate the board skews:

https://www.intel.com/content/www/us/en/programmable/solutions/technology/memory/estimator/board-skew.html

Regarding the debug, unfortunately, the Cyclone V HPS EMIF do not support the external memory interface toolkit. To debug the HPS EMIF, you can change the settings inside the preloader software to enable Runtime Calibration Report and Debug Level info. In addition, you can use the preloader software to check the status of HPS SDRAM PLL. Refer to Using the Preloader To Debug the HPS SDRAM on page 64 for more information. -->https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an-cv-av-soc-ddg.pdf

Hopefully this helps.

Thanks

Regards,

NAli1