Occasional Contributor
Occasional ContributorHi NAli1,
You have understood the whole thing perfectly.
The only thing left is to replace the FPGA. Rest all the components and connections have been verified. Even most have them have been assembled twice including DDR3.
Now, when I discussed here in INDIA with FAE from Cytech Macnica, they are telling that this can be due to timing issues due to board to board variation. They are telling that it may be so that
other boards have just passed marginally and this board is failing on the timing due to board to board variation. If that is the case of being so marginal, my customers are using my boards for last 6 months, at least once there should be a complaint on working boards.
We in my last 15 years have never seen a board working on 6 numbers [4 numbers is first stage and 2 numbers in second stage, with one left which is failing, I have to deliver total - 7] and then failing suddenly on one due to PCB variation and marginal timing issue. The difference between two stages was just an addition of a mounting hole at a remote corner.
If at all it is a marginal timing issue then how do I debug further, if at alll!!!
Occasional ContributorIf I have confused a little.
We had two stages of the board -
4 delivered in first stage and 3 in the second stage. In second stage only one mounting hole was added on one corner, no track modification. In second stage, 2 boards out of three are working. But overall DDR interface is untouched for all the 7 boards of which 6 are working and one left on which I have raised this question.
