DDR3 - CYCLONE V SOC FAILING ON HARDWARE

Hi HBhat2,

Thanks for the reply. I have also faced similar issues which have been tackled through assembly corrections on address lines.

In this case I have checked all and even replaced the components once even decoupling caps etc apart from term resistors, still no improvement.

I even bared VIAs below DDR3 to check for DDR3 data lines. All are showing an impedance value similar around 5.6K on a 20K DMM scale and so I am sure there is neither a DDR3 data lines shorting among each other nor there is a short with ground. Even, during calibration which eventually fails, all the data lines are showing toggling of data which removes my confusion that FPGA is disconnected with DDR3 on data path.

We have actually delivered 6 boards without any such problem. But this one has stuck the whole development for last 25 days.

I want to further read into this debugging messages to understand that whether we are actually on some timing margin issue. How to understand this further? Whether I can use EMI toolkit - I don't think so.