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SB_S's avatar
SB_S
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7 years ago

DDI Port mapping to FPGA Pins

For DDI port , should I need to use the transceiver pins(1C bank) or differential pins of 2L bank of 10AS016?
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

Thanks for your clarification on the net name in the A10 SOC devkit. As I understand it, the DDI port that you are referring are for Display Port. Based on my understanding with Display Port usage in A10 devices, generally they are connected to the high speed XCVR pins instead of GPIOs.

Please let me know if there is any concern. Thank you.

Chee Pin

SB_S's avatar
SB_S
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7 years ago

​okay, thanks Chee Pin

  • SB_S's avatar
    SB_S
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    7 years ago

    ​And also instead of 4 lanes of DDI ( Display port ) , can we use just 2 DDI lanes to connect the Display and does the Display Port IP supports the 2 lane implementation ?