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Aidin-P2D's avatar
Aidin-P2D
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

Cyclone V Unable to programme after .JIC file uploaded Error 209014

Hello everyone,

I was wondering if you help us with this issue. we have our custom FPGA board Cyclone V C5GTFD9E5F35I7 and the system was working fine with no issues until we decided to generate .jic file and programme it. the flash we are using is MT25QL256 Active serial AS4.

Initially, our design didn't have ant Nios II design and we successfully programmed .jic file and our flashing LEDs design was working fine. Then, we implemented Nios II processor to drive an LED flashing to indicate that Nios II is also booting fine. we generated .jic file and programmed the FPGA. then power cycle the FPGA and realised there were no flashing LEDs which indicating that system is failing to boot up. then we looked at design and decided to do another programming . However, since then we are unable to programme FPGA even with .sof file. the error message we are getting is

Error (209014): CONF_DONE pin failed to go high in device 1. Make sure all communication cables are securely connected, select a different device, check the power on the target system, or make sure all nCE pins are connected to GND. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

All voltage lanes are fine. USB blaster setup is successfully programmes other FPGAs so we are certain there is no issues with setup. we haven't altered any hardware and setup since the system was working correctly only change was to upload .jic file. any ideas why this could have happened greatly appreciated and how we can rescue our FPGA ? I should also mention that nCE pin is connoted to GND.

on the other note I should mention that we directly connect FPGA AS pins to MT25QL256. I realised that on most DEV boards, there is an analog switch for isolating Flash. the fact that we are not isolating Flash, could cause this issue? Thanks

Regards,

Aidin.

Board Debug
  • FvM's avatar
    FvM
    1 year ago

    Hi,

    presume you are testing .sof files (without Nios) taht worked before. Did you also to try to erase flash in .jic programming mode, using fac tory default SFL?

    There might be a problem that FPGA is continously trying to load invalid AS data. In this case, you try programmer option "halt on-chip configuration controller".

    Connecting

    Regards,
    Frank

2 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,

    presume you are testing .sof files (without Nios) taht worked before. Did you also to try to erase flash in .jic programming mode, using fac tory default SFL?

    There might be a problem that FPGA is continously trying to load invalid AS data. In this case, you try programmer option "halt on-chip configuration controller".

    Connecting

    Regards,
    Frank

  • Aidin-P2D's avatar
    Aidin-P2D
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hi Frank,

    Thanks for your comment. the later was the case as we wrongly configure the system to use USRCLK and because we didn't have such a clock , system was continually trying to load AS data.

    unfortunately, I didn't try your solution and we just supplied with clock before seeing your post. however, what JTAG was unable to configure the tool / is there any way we can interrupt this ?

    below is the our JTAG connector and I wonder if we can change this to interrupt FPGA ?

    for example will connecting like below help avoiding this issue ?

    on the other note, we have MT25QL256 as a flash and question is will EPCQ256 IP core work with MT25Q256? FPGA .sof file configures correctly but so far I wasn't able to boot NIOS II from this device. any comments and thoughts greatly appreciated.

    Regards,

    Aidin.