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Aidin-P2D's avatar
Aidin-P2D
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

Cyclone V Unable to programme after .JIC file uploaded Error 209014

Hello everyone, I was wondering if you help us with this issue. we have our custom FPGA board Cyclone V C5GTFD9E5F35I7 and the system was working fine with no issues until we decided to generate .ji...
Board Debug
  • FvM's avatar
    FvM
    1 year ago

    Hi,

    presume you are testing .sof files (without Nios) taht worked before. Did you also to try to erase flash in .jic programming mode, using fac tory default SFL?

    There might be a problem that FPGA is continously trying to load invalid AS data. In this case, you try programmer option "halt on-chip configuration controller".

    Connecting

    Regards,
    Frank

Aidin-P2D's avatar
Aidin-P2D
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi Frank,

Thanks for your comment. the later was the case as we wrongly configure the system to use USRCLK and because we didn't have such a clock , system was continually trying to load AS data.

unfortunately, I didn't try your solution and we just supplied with clock before seeing your post. however, what JTAG was unable to configure the tool / is there any way we can interrupt this ?

below is the our JTAG connector and I wonder if we can change this to interrupt FPGA ?

for example will connecting like below help avoiding this issue ?

on the other note, we have MT25QL256 as a flash and question is will EPCQ256 IP core work with MT25Q256? FPGA .sof file configures correctly but so far I wasn't able to boot NIOS II from this device. any comments and thoughts greatly appreciated.

Regards,

Aidin.