Forum Discussion

New Contributor

6 years ago

Cyclone V Transceiver PHY Basic Design Examples

Hello, i need the examples designes in this page : https://forums.intel.com/s/createarticlepage?language=en_US&articleid=a3g0P0000005QydQAE&artTopicId=0TO0P000000MWKBWA4&action=view The links don...

S_Healthineers

New Contributor

6 years ago

Hi ,

wand the Cyclone V Native PHY with manual alignment design example

Thanks

Forum Discussion

Cyclone V Transceiver PHY Basic Design Examples

Recent Discussions

SyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series design

PCIe Root Complex on DK-A5E013BM16AEA

Agilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_Altera

Agilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPs

R-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK_DEV_AGM039EA) does not work