Forum Discussion

Chandrashekhar_K's avatar
Chandrashekhar_K
Icon for New Contributor rankNew Contributor
2 years ago

Cyclone V SoC DDR3 Not working

On custom board we are trying to make the DDR3 up. I'm trying to debug the preloader and check the DDR3 working.
Have generated handoff files from Quartus prime. Compiled using BSP editor settings and finally generated uboot-spl file.

Attached are the DDR3 memory parameters and the error I get while debugging the preloader.

DDR3 part no MT41K256M16TW-107IT:P
Cyclone V Part no 5CSEBA5U23I7
Quartus 18.1
SoCEDS DS-5 v5.29.1

As the DDR3 is backward compatible to DDR3L-1600, I have used the same SDRAM settings avaialbe in the CV GSRD example. The board setting and the skew values are the defaults

I'm not able to make the DDR3 up.

The following troubleshooting is done |
1. The regulators outputs for VTT(0.75V), VREF(0.75V) and 1.5V required for DDR3 are at required voltage levels
2. Clock and Reset are OK
3. Schematics are checked and found OK.
4. Able to run hello world example from on chip ram.
5. Very rarely I get the debug message as in the text file attachement

Kindly help to reolve the issue to make the DDR3 Up.

Fpga Devkit

3 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hello,


    Have you checked if the DDR3 components are working on the board with FPGA EMIF interface?


    Regards,

    Adzim


  • Chandrashekhar_K's avatar
    Chandrashekhar_K
    Icon for New Contributor rankNew Contributor
    2 years ago

    We were able to resolve the issue and the DDR3 is working now.

    The BELSEL pins are set to boot from QSPI. There was no valid image in QSPI and after connecting the JTAG to debug the preloader, we were able to observer the Chip Select pin kept on asserting. (I understand the JTAG should take priority and CS assertion should stop).

    We flashed some image and then could observe the CS pin not asserting after connecting JTAG. Still we were not able to make the DDR up in debug mode.

    Finally disabled the semihosting feature and enabled the serial support in bsp editor and flashed the compiled u-boot spl image to QSPI We were able to see the the ddr3 being calibrated message in teraterm

    After this we were able to debug the preloader with semihosting enabled.

    Still not clear with the points

    1. The start address the CV Soc kit shows when loading the spl and custom board are different. I think it should be same as the start address after reset will be same for the HPS core.

    2. Why there should be some image in boot device to debug the preloder?

    3. Why CS keeps asserting even after connecting JTAG without a valid image in it.

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hello,


    I'm glad to hear that your issue has been resolved.


    For your follow up questions, you may create another thread to get some clarification from the Intel experts because I'm not familiar with the booting FPGA side.

    I'm fine to kept this thread open for DDR related question.

    Otherwise I will leave this thread to community users to help you on this thread.


    Regards,

    Adzim