Cyclone V: reaching RGMII Data to Clock output skew of +/- 500ps

Hi Sheng,

Correct, even without the tracedelay (Combination 1), the setup fails.

"Could you try with PHY with delay option disabled, does the timing pass?"

But I do need the PHY-delay to shift the data from edge- to center-aligned. Without, timing will fail massivley.

...and did faild massively.

Again, what jitter at the Cyclone V is to be expected for such a combination of both, data and clk coming from ddio-buffer?

Could you please share with me what jitter is to expect.

Does the fpga maybe struggle to delay the data singals internally positive or negative to the clock signal?

Could I help the synthesis tool by shifting the external PHY-delay away from symmetric (2ns) towards a asymmetrical delay for example (+/- 1.5ns). But this is basically what I tried to achive before and failed.