Cyclone V: reaching RGMII Data to Clock output skew of +/- 500ps

Hi,

I think you can refer the timing constraints in AN477: Designing RGMII Interface with FPGA and HardCopy Devices (page 12) https://www.intel.com/content/www/us/en/content-details/654563/an-477-designing-rgmii-interface-with-fpga-and-hardcopy-devices.html

The internal PHY delay is considered in tco for set_input_delay

For the equation in this link https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/exm-tse-rgmii-phy.html, $data_delay_min, $data_delay_max, $clk_delay_min, $clk_delay_max put 0 as assume trace delay, pin capacitance, and rise/fall time differences between data and clock are negligible

Design .qar can be found here https://blog.csdn.net/wangyanchao151/article/details/90401027

Let me know if any further update or concern.

Thanks,

Regards,

Sheng