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Fjato
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6 years ago

Cyclone V QSys-design only working when set as top-level entity

Hi there, I am currently experimenting with a Cyclone V SoC (DE10-Nano-SoC Kit). Therefore, I implemented parts of the design with the help of QSys including Clock, HPS, PIO, SPI and JTAG UART, gene...
Fjato's avatar
Fjato
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6 years ago

Hi and thanks for your reply.

In the mean time, I found the solution for my problem. I did export "memory" and "hps_io" within qsys, but I did not connect any ports to it in quartus. After correcting this, the compilation runs perfectly. Furthermore, I switched from the block symbol design to textual design, even if it was not the root cause of my problem, but it feels more convenient.

However, thanks for your hep and best regards.