Cyclone V QSys-design only working when set as top-level entity
Hi there,
I am currently experimenting with a Cyclone V SoC (DE10-Nano-SoC Kit). Therefore, I implemented parts of the design with the help of QSys including Clock, HPS, PIO, SPI and JTAG UART, generated the HDL code and a .bsf file (block symbol file) and imported the files in qartus.
a) When setting the corresponding .qip-file (Qartus Prime IP file) as top-level entity, everything works fine.
b) When setting up a Block Diagram / Schematic file as top-level entity which includes the above-mentioned QSys-Design as block symbol, the fitter shows the following error.
Error: The auto-constraining script was not able to detect any instance for core < hps_sdram_p0 >
Error: Verify the following:
Error: The core < hps_sdram_p0 > is instantiated within another component (wrapper)
Error: The core is not the top-level of the project
Error: The memory interface pins are exported to the top-level of the project
What am I doing wrong? Please let me know, if further information is required.
Thanks and best regards