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NAdel1's avatar
NAdel1
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6 years ago

Cyclone V, problem when the JTAG configuring flash MT25QL256(micron) with .jic

I understand that the jtag puts some SPI controller in the FPGA to talk to the flash, but i see that before the jtag configuring the flash, the FPGA check something in the flash before it puts .jic i...
NAdel1's avatar
NAdel1
Icon for New Contributor rankNew Contributor
6 years ago

​Thanks for your response.

I understand that the flash's Non-Volatile Register is configuring during the process.

My question is more specific, the SPI controller that the JTAG puts in the FPGA read something from the flash and if it don’t like it, the 'flash loading' "failed".

What the SPI controller reading before loading the flash?

ShafiqY_Intel's avatar
ShafiqY_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi NAdel1,

I'm apologize for late reply. I'm AFK for couple of days.

To understand better regarding this, go to Quartus > File > Convert Programming File.. In Programming file type option choose JTAG Indirect Configuration file (.JIC).... Then, select "..." option:

Then, you select the reference for MT25Q01G device

Here, you can understand how it have been Initialization, Program, Erase, Verif/Blank-Check/Examine, and termination.

I hope found this informative.

NOTED: This feature only avalaible in Quartus 18.1.1 (standard version) / Quartus 19.1 (pro version) onwards.

Cheers.