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New Contributor

6 years ago

Cyclone V: leakage current of Vref pins

Hello, I'm designing a very compact design with a 5CEFA4 Cyclone V FPGA and a single DDR3 chip. Following the Micron and Intel guidelines, I chose to not use VTT termination and to use only a simpl...

Rahul_S_Intel1

Frequent Contributor

6 years ago

Hi Zak,

Kindly find the KDB for your reference, as I mentioned the leakage is only characterized for the IO, as per me the same can be considered for VREF . Kindly find the KDB for your reference.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd11122003_7976.html?wapkw=vref%20leakage

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Cyclone V: leakage current of Vref pins

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