Cyclone V Frame Buffer II - problem with device Tree and with understanding the address map

Repost previous comments:

Hi Jakej,

I am using the example design shown in the link below to describe to you regarding how the address works for frame buffer IP:

https://fpgacloud.intel.com/devstore/platform/1986/

Normally for the frame buffer will get the data from some memory location which determined by the user, example from ddr4 in the qsys design shown in the pic below.

The Frame buffer will get the image data from the ddr4, therefore the frame buffer memory base address must follow the based address of the location which stores your image data.

The frame buffer IP will not have a base address unless you require to control it's register settings during run time.

If there is no requirement to make changes during run time, then set the frame buffer IP settings in the qsys will do for your design.

You can enable the Run-time writer control shown in the example pic below. The details of the control handling will relates back to the document regarding frame buffer IP.

Hopefully it helps.

Thanks.

Regards,

Aik Eu