Honored Contributor
Honored ContributorTestbench which was generated from SOPC does work. Apparently, SOPC flow example is not really simple. I'm sure I'm repeating someone's footsteps.
This is from mySupport regarding SOPC flow. -------------------------------------------------------------------------- 1. Generate free running 50MHz reconfig_clk and 125MHz fixedclk. They both should NOT be derived from 100MHz refclk or its derived clocks. PCIe UG Figure 7-1 shows these clocks connection, it uses a free running 100MHz and derive fixedclk & reconfig_clk through GPLL. http://www.altera.com/literature/ug/ug_pci_express.pdf?#page=178 2. Created the reconfig_blk and before compiling Quartus II design, regenerate the reconfig_blk with input offset_cancellation_reset port. The reconfig block is needed for transceiver offset cancellation. To generate this port, run the following command (using Windows command prompt and cd to project reconfig.v file location): qmegawiz -silent -wiz_override="offset_cancellation_reset" <altgx_reconfig filename.v> Kindly refer below solution for more details on reconfig_clk and offset_cancellation_reset connection. http://www.altera.com/support/kdb/solutions/rd12172009_309.html 3. Keep reconfig block in reset (assert offset_cancellation_reset input) until both reconfig_clk and fixedclk are stabled. For example, if both of this clocks are derived from the same PLL, then offset_cancellation_reset = !(pll_locked) In other words, the offset_cancellation_reset is the invertion of "pll_locked" (a NOT Gate in between). See Figure 7–1. 'Internal Reset Modules in the Hard IP Implementation' of the PCIe User Guide for the illustration. 4. Connect the busy signal of reconfig block to the busy_altgxb_reconfig input of the PCIe block. -------------------------------------------------------------------------- I need to try this out. Not sure to generate reconfig_clk and fixedclk in SOPC or seperate module.
