Cyclone III Starter Kit - DDR-SDRAM - help

What exactly does not work? Are there any error messages? Did you try the "Hello NIOS" example and does it run correctly? I`m not sure if the SDRAM is connected in the standard_sopc file. If it is the NIOS CPU use it to store your data or code in it. So you can write something into RAM by writing something like:

int a = 42;

Or do you mean something different and I´m sure you do.

My really question is:

I want to write and to read in ddr-sdram.

I have four options:

*Implement all logic by "hand" (in code VHDL);

*Use the SOPC Builder for start the project from 'zero';

*Change the QB3 Control Painel example;

*Change the CycloneIII_3c25_start_niosII_standard example.

Changing the QB3 Control Painel example, I don't have the SOPC Builder System PTF file for implement my code in Nios II. And I don't get to create this file.

Changing the CycloneIII_3c25_start_niosII_standard example, my project have only: Nios II processor,DDR-SDRAM controller,jtag,onchip memory and led pio.

I compile the project, and in the Nios software, I program this code:

int main(void)

{

int ch;

int a,b,c,d;

int memory_base = 0x02000000;

/* Print the Header */

MenuHeader();

/* Print the menu and do what the user requests, until they hit 'q' */

while (1)

{

IOWR_8DIRECT(memory_base, 0, 0x0A);

IOWR_8DIRECT(memory_base, 1, 0x05);

IOWR_8DIRECT(memory_base, 2, 0xA0);

IOWR_8DIRECT(memory_base, 3, 0x50);

a = IORD_8DIRECT(memory_base, 0);

b = IORD_8DIRECT(memory_base, 1);

c = IORD_8DIRECT(memory_base, 2);

d = IORD_8DIRECT(memory_base, 3);

printf( "\nmemory 1 = %d.\n",a);

printf( "\nmemory 2 = %d.\n",b);

printf( "\nmemory 3 = %d.\n",c);

printf( "\nmemory 4 = %d.\n",d);

//ch = TopMenu();

if (ch == 'q')

{

printf( "\nExiting from Memory Test.\n");

break;

}

}

return (0);

}

But, when I run this, appears a error:

Verifying 02000000 ( 0%)

Verifying 02010000 (83%)

Verifying 04001020 (99%)

Verify failed between address 0x4001020 and 0x40011C7

Leaving target processor paused

Someone help me ?

Before tihe, I tried to test the memory test template of Nios II and I don't have success too.

Deleting the on_chip memory, appears:

Initializing CPU cache (if present)

OK

Downloading 02000000 ( 0%)

Downloading 02010000 (83%)

Downloaded 78KB in 1.3s (60.0KB/s)

Verifying 02000000 ( 0%)

Verifying 02010000 (83%)

Verified OK

Leaving target processor paused

I really lost now. rs

First you must launch Timequest to check that all the I/O are constrained. Then you can either check if the timing requirements are met in Timequest, or by looking at the critical warnings when you compile your Quartus project.

What changes did you do to the CycloneIII_3c25_start_niosII_standard? I assume the standard example is properly constrained.

Hi

I faced problem when running CycloneIII_3c25_start_niosII_standard. I have Verify address failed problem. The address is pointing to sdram. Could anyone help?

Thanks

i tried running memory test template from Nios II. It appears memory bit failed to be verified at data bit 0x01 sort of msg in console. if that's the case, how can i debug it?

thanks,

caridee