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Your best bet is to take the exact device partnumber and look up the datasheet on the web. Micron for example explains in great detail how their SD-RAMs work, how to operate them and so on and so on. Step 1 is to learn to understand the device.
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The part number of my DDR-SDRAM Chip is
psc a2s56d40ctp. I already found the datasheet (
http://wiki.laptop.org/images/4/43/a2s56d40ctp-g5.pdf), but it was not very useful for me.
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I did the same for the ISSI SRAM on the board (much simpeler than DDR SDRAM but the process is the same) and wrote a controller around it after I understood exactly how the SRAM works.
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It seems that writing a controller for DDR-SDRAM from scratch would be a too big project. As I don't have that much time, I decided to use the existing IP-cores from Altera.
Yesterday, I spent some time searching in the forum and reading the ddr and ddr2 sdram high-performance controller user guide (
http://www.altera.com/literature/ug/ug_ddr_ddr2_sdram_hp.pdf). When I had not really success, I took the
qb3_control_panel sample project and modified it a little bit. In the attachment you can see a screenshot of the block diagram file. I don't understand where the input pins for the data, commands, adress, etc. are. It looks like a
closed circuit. I thought these blocks are some kind of
driver for users like me, that don't want to write a ddr-controller from scratch. But how could I use this...? Which pins should I use?
What does this
ez_cmdecoder...?
Has anyone already worked with
ddr_cntr and knows something about these pins and signals like
dec_nwr,
ddram_data[63..0] or
dec_byen[7..0] ?
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