New Contributor
Super ContributorHi
I am not sure on what is the specific enquiry and your plans to do here but the board design management chip (Max 10) here is proprietary design which is beyond dev kit support coverage. Intel mainly sells the dev kit to promote FPGA device and FPGA feature usage but the board design. We support on FPGA related enquiry, but board design is different topic.
New ContributorIt's not about system management chip (Max 10) design or internals.
The Cyclone 10LP kit does not provide any USB connections to the user designs in the Cyclone 10LP fpga.
Seeing the set of usb-related lines on a schematics, and seeing same lines defined as regular IO in the gold reference design project I realized I could use that interface to communicate with my designs, implementing own IPs to serve the USB transfers on those lines.
Since the lines are not connected to any dedicated hardware functionality on the Cyclone 10LP fgpa I came to a conclusion that interface requires an IP to be implemented on the fpga side, so from the very beginning this interface was intended to be used for communications with the user designs in Cyclone 10LP fpga over the USB, regardless of the implementation details of the system management facilities.
It's unfortunate the protocol between USB endpoints and usb-related lines going into Cyclone 10LP is not described. I'm not asking for designs or IPs, just the definition of the protocol which must exist, because same interface is found on two different Intel fpga kits. And I thought since this is a board for "FPGA/SoC/CPLD boards and kits" discussions, someone could shed some light on that particular detail of the Cyclone 10LP evaluation kit.
